1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to a fused delay circuit for use in such integrated circuit devices.
2. Description of the Prior Art
Integrated circuits, especially high speed devices such as EPROMs, microprocessors, gate arrays, and memory devices, are optimally designed to operate as fast as possible. Devices which are marketed as slower version,,; of these high speed devices may or may not be slower, and often retain the high speed characteristics of the fastest device. For this reason, customers often purchase "slower" versions of a high speed device at a discount, and simply characterize and speed-sort the devices to determine which devices are actually "fast". Such an endeavor can be quite advantageous for the purchaser, due to the high premium price typically charged for the fastest speed grade part.
From an engineering perspective, devices branded as slow devices that are actually a fast speed grade can cause difficulties in the circuitry in which they are used. Often devices must meet the electrical parameters required by a slower application. For instance, timing problems can result when the proper hold time and set-up time for a device is not achieved.
To date, there have been few feasible methods available to effectively slow down integrated circuits. Mask changes may be used to slow down a fast device by adding additional logic gates or other circuitry to the mask set. Using this method, a new mask set is required for every speed grade of the device. Unfortunately, mask changes also require extensive design time and are therefore costly in terms of time and money expended. For these economical and engineering reasons, it would be desirable in the art to slow down the speed of an integrated circuit with a minimum amount of time, effort, and expense.